Generally, a LCD panel comprises plural gate lines. In addition, plural gate driving signals are sequentially received by the gate lines, and thus the pixels connected with the gate lines are sequentially turned on.
FIG. 1A is a schematic circuit diagram illustrating a multiplex driving circuit. FIG. 1B is a schematic timing waveform diagram illustrating associated signal processed by the multiplex driving circuit of FIG. 1A. As shown in FIG. 1A, the signals A1˜A4 may be referred as master signals, and the signals ENB1y˜ENB3y may be referred as slave signals. The master signals A1˜A4 are generated by a shift register 500.
As shown in FIG. 1B, the master signals A1˜A4 that are non-overlapped pulses with the same width are sequentially generated. Each of the slave signals ENB1y˜ENB3y includes plural pulses with the same frequency but different phases. Please refer to FIG. 1B. A cycle period of each slave signal is equal to the pulse width of each master signal. In the three slave signals ENB1y˜ENB3y, the duty cycle of each slave signal is ⅓, and the phase difference between every two adjacent slave signals is 120 degrees (i.e. 360/3=120).
Please refer to FIG. 1A again. Each master signal is transmitted to three driving stages 502. In addition, the slave signals are received by respective driving stages 502. Consequently, these driving stages sequentially output respective gate driving signal Y1˜Y6, . . . , and so on. As shown in FIG. 1A, each driving stage of the multiplex driving circuit comprises a NAND gate 503 and an inverter 504. In other words, each driving stage of the multiplex driving circuit is implemented by many transistors.